A scalable architecture of a structured LDPC decoder

被引：0

作者：

Lee, JKS ^{[1
]}

Lee, B ^{[1
]}

Thorpe, J ^{[1
]}

Andrews, K ^{[1
]}

Dolinar, S ^{[1
]}

Hamkins, J ^{[1
]}

机构：

[1] CALTECH, Jet Prop Lab, Pasadena, CA 91125 USA

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a scalable decoding architecture for a certain class of structured LDPC codes. The codes are designed using a small (n, r) protograph that is replicated Z times to produce a decoding graph for a (Z x n, Z x r) code. Using this architecture, we have implemented a decoder for a (4096,2048) LDPC code on a Xilinx Virtex-II 2000 FPGA, and achieved decoding speeds of 31 Mbps with 10 fixed iterations. The implemented message-passing algorithm uses an optimized 3-bit non-uniform quantizer that allows near floating point performance in the waterfall region, with drastically smaller hardware implementation requirements.

引用

页码：292 / 292

页数：1

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