Developing 13-kV 4H-SiC MOSFETs: Significance of Implant Straggle, Channel Design, and MOS Process on Static Performance

13-kV 4H-SiC MOSFETs were successfully fabricated on a 125-mu mu-thick epitaxial layer on 6-in, N+ SiC substrates. Both lateral and longitudinal straggles from the P-well implant were investigated to optimize the JFET width and thus to avoid channel pinching in the JFET region. Channel lengths and channel mobilities were varied to investigate the effect of channel portions in determining the ON-state resistance of the 13-kV MOSFETs. It was discovered that the low channel mobility limits the transconductance, such that the MOSFETs cannot offer full current at reasonable gate voltages (V-gs = similar to 20 V). Even in high voltage MOSFETs, it is essential to have a reasonably high channel mobility to reduce ON-state power loss. Therefore, channel design and process are also important aspects of high voltage devices. A superior blocking capability of 13.2 kV was demonstrated using a ring-based edge termination structure. It is important to note that the straggling effect due to ion implantations should also be taken into account when designing an edge termination structure. Static electrical characteristics, scanning electron microscope (SEM) imaging, secondary ion mass spectrometry (SIMS) analysis, and 2-D simulation of the 13-kV MOSFETs were employed to support this reasoning.