FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects

被引:76
作者
Cong, Jason [1 ,2 ]
Xiao, Bingjun [1 ]
机构
[1] Univ Calif Los Angeles, Dept Elect Engn & Comp Sci, Los Angeles, CA 90095 USA
[2] Calif Nanosyst Inst, Los Angeles, CA 90095 USA
关键词
Emerging device; field programmable gate array (FPGA); programmable interconnects; reconfigurable logic; resistive random access memory (RRAM); LOW-POWER;
D O I
10.1109/TVLSI.2013.2259512
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper we introduce a novel field programmable gate array (FPGA) architecture with resistive random access memory (RRAM)-based programmable interconnects (FPGA-RPI). Programmable interconnects are the dominant part of FPGA. We use RRAMs to build programmable interconnects, and optimize their structures by exploiting opportunities that emerge in RRAM-based circuits. FPGA-RPI can be fabricated by the existing CMOS-compatible RRAM process. Using an advanced placement and routing tool named VPR-RPI which was developed to deal with the novel architecture, a customized CAD flow is provided for FPGA-RPI. Results show that the programmable interconnects of FPGA-RR have a 96% smaller footprint, 55% higher performance, and 79% lower power consumptions compared to other FPGA counterparts.
引用
收藏
页码:864 / 877
页数:14
相关论文
共 53 条
[1]   The effect of LUT and cluster size on deep-submicron FPGA performance and density [J].
Ahmed, E ;
Rose, J .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (03) :288-298
[2]   A practical methodology for early buffer and wire resource allocation [J].
Alpert, CJ ;
Hu, J ;
Sapatnekar, SS ;
Villarrubia, PG .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2003, 22 (05) :573-583
[3]   Low Write-Energy Magnetic Tunnel Junctions for High-Speed Spin-Transfer-Torque MRAM [J].
Amiri, P. Khalili ;
Zeng, Z. M. ;
Upadhyaya, P. ;
Rowlands, G. ;
Zhao, H. ;
Krivorotov, I. N. ;
Wang, J. -P. ;
Jiang, H. W. ;
Katine, J. A. ;
Langer, J. ;
Galatsis, K. ;
Wang, K. L. .
IEEE ELECTRON DEVICE LETTERS, 2011, 32 (01) :57-59
[4]  
[Anonymous], VIRT 6 FPGA CONF LOG
[5]  
[Anonymous], IEDM
[6]  
[Anonymous], 2009, VIRT 4 FPGA DAT SHEE
[7]  
Betz V., 1999, Architecture and CAD for Deep-Submicron FPGAs
[8]  
Bruchon N, 2006, IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, P269
[9]  
Burger D., 2011, INT TECHNOLOGY ROADM
[10]   Low-power hybrid complementary metal-oxide-semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping [J].
Chakraborty, R. S. ;
Paul, S. ;
Zhou, Y. ;
Bhunia, S. .
IET COMPUTERS AND DIGITAL TECHNIQUES, 2009, 3 (06) :609-624