A Survey and Analysis on SoC Platform Security in ARM, Intel and RISC-V Architecture

被引:0
|
作者
Nicholas, Geraldine Shirley [1 ]
Gui, Yutian [1 ]
Saqib, Fareena [1 ]
机构
[1] Univ N Carolina, Dept Elect & Comp Engn, Charlotte, NC 28223 USA
关键词
RISC-V; ARM TrustZone; Intel SGX; Trusted Execution Environment (TEE); BOOT;
D O I
10.1109/mwscas48704.2020.9184573
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Modern heterogeneous computing including IoT devices and Networks deliver optimized and enhanced performance along with high speed but rely on an increased number of components to achieve the desired results. The design productivity for hardware accelerators with machine learning platforms for various application has significant progress on system-on-chip architectures. Most of these technologies provide the desired performance, however, there is always a tradeoff between security and performance. The major role in developing frameworks for hardware security attacks depends on the IP and system architecture. RISC-V provides a platform for custom implementation of security extensions when compared to other traditional architectures. This paper provides a brief survey of different hardware/ software security attacks and summarizes a comparison of security features in RISC-V and other traditional architectures along with security extensions that can be achieved by RISC-V.
引用
收藏
页码:718 / 721
页数:4
相关论文
共 50 条
  • [21] Comprehensive analysis of energy efficiency and performance of ARM and RISC-V SoCs
    Suarez, Daniel
    Almeida, Francisco
    Blanco, Vicente
    JOURNAL OF SUPERCOMPUTING, 2024, 80 (09): : 12771 - 12789
  • [22] Is RISC-V ready for Space? A Security Perspective
    Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Italy
    不详
    不详
    不详
    不详
    Proc. IEEE Int. Symp. Defect Fault Toler. VLSI Nanotechnol. Syst., DFT,
  • [23] Securing a RISC-V architecture: A dynamic approach
    Pillement, S.
    Real, M. Mendez
    Pottier, J.
    Nieddu, T.
    Le Gal, B.
    Faucou, S.
    Bechennec, J. L.
    Briday, M.
    Girbal, S.
    Le Rhun, J.
    Gilles, O.
    Perez, D. Gracia
    Sintzoff, A.
    Coulon, J. R.
    2023 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE, 2023,
  • [24] Trusted Hart for Mobile RISC-V Security
    Ushakov, V.
    Sovio, S.
    Qi, Q.
    Nayani, V.
    Manea, V.
    Ginzboorg, P.
    Ekberg, J. E.
    2022 IEEE INTERNATIONAL CONFERENCE ON TRUST, SECURITY AND PRIVACY IN COMPUTING AND COMMUNICATIONS, TRUSTCOM, 2022, : 1587 - 1596
  • [25] Towards a Heterogeneous Fault-Tolerance Architecture based on Arm and RISC-V Processors
    Rodrigues, Cristiano
    Marques, Ivo
    Pinto, Sandro
    Gomes, Tiago
    Tavares, Adriano
    45TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY (IECON 2019), 2019, : 3112 - 3117
  • [26] Architectural Security and Trust Foundation for RISC-V
    Boubakri, Marouene
    Zouari, Belhassen
    2024 IEEE 27TH INTERNATIONAL SYMPOSIUM ON REAL-TIME DISTRIBUTED COMPUTING, ISORC 2024, 2024,
  • [27] The Implementation of LeNet-5 with NVDLA on RISC-V SoC
    Feng, Shanggong
    Wu, Junning
    Zhou, Shengang
    Li, Renwei
    PROCEEDINGS OF 2019 IEEE 10TH INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING AND SERVICE SCIENCE (ICSESS 2019), 2019, : 39 - 42
  • [28] A Custom Designed RISC-V ISA Compatible Processor for SoC
    Sharat, Kavya
    Bandishte, Sumeet
    Varghese, Kuruvilla
    Bharadwaj, Amrutur
    VLSI DESIGN AND TEST, 2017, 711 : 570 - 577
  • [29] A Survey on Thwarting Memory Corruption in RISC-V
    Brohet, Marco
    Regazzoni, Francesco
    ACM COMPUTING SURVEYS, 2024, 56 (02)
  • [30] SMARTS: Secure Memory Assurance of RISC-V Trusted SoC
    Wong, Ming Ming
    Haj-Yahya, Jawad
    Chattopadhyay, Anupam
    PROCEEDINGS OF THE 7TH INTERNATIONAL WORKSHOP ON HARDWARE AND ARCHITECTURAL SUPPORT FOR SECURITY AND PRIVACY (HASP '18), 2018,