Fast Locking and High Accurate Current Matching Phase-Locked Loop

被引：4

作者：

Liu, Silin ^{[1
]}

Shi, Yin ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Semicond, Beijing 100083, Peoples R China

来源：

2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 | 2008年

关键词：

D O I：

10.1109/APCCAS.2008.4746225

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PILL circuit is designed based on the 0.35um 2P4M CMOS process with 3.3V/5V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PILL and its charge pump sink and source current mismatch is only 0.008%.

引用

页码：1136 / 1139

页数：4

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