A New Latch Comparator with Tunable Hysteresis

Hysteresis is basically a circuit nonideality but in some applications it is used to prevent the comparator's outputs from toggling back and forth between logic levels when solving small inputs in noisy environments. This paper presents an enhanced latch comparator where hysteresis can be handled and adjusted to specific values. A frequency domain analysis of the latch comparator operating at the beginning of the comparison process is performed and has shown to be efficient in predicting hysteresis and circuit behavior at high clock frequencies. In the light of the predicted features, a new latch comparator has been proposed to enhance hysteresis and speed and was designed using a commercially available 0.18 mu m CMOS technology. It operates under a power supply of 1.8V, with a clock frequency of 800MHz and consumes an average power of about 90 mu W. Compared to the common basic structure when considering a 1.4mV hysteresis, simulation results of the proposed comparator have shown that hysteresis can be easily adjusted to about 300 mu V without trading design complexity or time delays.