Linewidth effect and phase control in Ni fully silicided gates

被引:14
作者
Kittl, J. A. [1 ]
Lauwers, A.
Hoffmann, T.
Veloso, A.
Kubicek, S.
Niwa, M.
van Dal, M. J. H.
Pawlak, M. A.
Demeurisse, C.
Vrancken, C.
Brijs, B.
Absil, P.
Biesemans, S.
机构
[1] IMEC, B-3001 Heverlee, Belgium
[2] Philips Res Leuven, B-3001 Louvain, Belgium
关键词
full silicidation; fully silicided (FUSI); high-k dielectric; metal gate; MOSFET; NiSi; Ni2Si; Ni31Si12; short channel; V-t rolloff;
D O I
10.1109/LED.2006.879036
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni2Si, and Ni31Si12. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and V-t control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni2Si processes with excessive thermal budgets, resulting in significant Vt shifts for devices on HfSiON consistent with the difference in work function among the Ni silicide phases. Linewidth-independent phase control with smooth V-t rolloff characteristics was demonstrated for NiSi, Ni2Si, and Ni31Si12 FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). Phase characterization over a wide temperature range indicated that the process windows for scalable NiSi and Ni2Si are less than or equal to 25 degrees C, whereas a single-phase Ni31Si12 is obtained over an -200 degrees C temperature range.
引用
收藏
页码:647 / 649
页数:3
相关论文
共 6 条
[1]  
Anil KG, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P190
[2]  
Cabral C, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P184
[3]  
Kittl JA, 2005, 2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P72
[4]   Work function of Ni silicide phases on HfSiON and SiO2:: NiSi, Ni2Si, Ni31Si12, and Ni3Si fully silicided gates [J].
Kittl, JA ;
Pawlak, MA ;
Lauwers, A ;
Demeurisse, C ;
Opsomer, K ;
Anil, KG ;
Vrancken, C ;
van Dal, MJH ;
Veloso, A ;
Kubicek, S ;
Absil, P ;
Maex, K ;
Biesemans, S .
IEEE ELECTRON DEVICE LETTERS, 2006, 27 (01) :34-36
[5]  
Maszara WP, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P367, DOI 10.1109/IEDM.2002.1175854
[6]   Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices [J].
Takahashi, K ;
Manabe, K ;
Ikarashi, T ;
Ikarashi, N ;
Hase, T ;
Yoshihara, T ;
Watanabe, H ;
Tatsumi, T ;
Mochizuki, Y .
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :91-94