A Reconfigurable Hardware for One Bit Transform based Multiple Reference Frame Motion Estimation

被引:0
作者
Akin, A. [1 ]
Sayilar, G. [1 ]
Hamzaoglu, I. [1 ]
机构
[1] Sabanci Univ, Fac Engn & Nat Sci, TR-34956 Istanbul, Turkey
来源
2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010) | 2010年
关键词
Motion Estimation; One Bit Transform; Multiple Reference Frame; Hardware Implementation; FPGA; SELECTION ALGORITHM; INTERPOLATION;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose a high performance reconfigurable hardware architecture of 1BT based multiple reference frame (MRF) ME. The proposed ME hardware architecture performs full search ME for 4 Macroblocks and 4 reference frames in parallel. The proposed hardware is faster than the 1BT based ME hardware reported in the literature even though it is capable of searching in 4 reference frames. MRF ME increases the ME performance at the expense of increased computational complexity. The reconfigurability of the proposed ME hardware is used to statically configure the number and selection of reference frames based on the application requirements in order to trade-off ME performance and computational complexity. The proposed hardware architecture is implemented in Verilog HDL. The MRF ME hardware consumes %65 of the slices in a Xilinx XC2VP30-7 FPGA. It can work at 191 MHz in the same FPGA and is capable of processing 83 1920x1080 full High Definition frames per second.
引用
收藏
页码:393 / 398
页数:6
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