A highly manufacturable 110nm DRAM technology with 8F2 vertical transistor cell for 1Gb and beyond

被引：3

作者：

Akatsu, H ^{[1
]}

Weis, R ^{[1
]}

Cheng, K ^{[1
]}

Seitz, M ^{[1
]}

Kim, MS ^{[1
]}

Ramachandran, R ^{[1
]}

Dyer, T ^{[1
]}

Kim, B ^{[1
]}

Kim, DK ^{[1
]}

Malik, R ^{[1
]}

Strane, J ^{[1
]}

Goebel, T ^{[1
]}

Kwon, OJ ^{[1
]}

Sung, CY ^{[1
]}

Parkinson, P ^{[1
]}

Wilson, K ^{[1
]}

McStay, I ^{[1
]}

Chudzik, M ^{[1
]}

Dobuzinsky, D ^{[1
]}

Jacunski, M ^{[1
]}

Ransom, C ^{[1
]}

Settlemyer, K ^{[1
]}

Economikos, L ^{[1
]}

Simpson, A ^{[1
]}

Knorr, A ^{[1
]}

Naeem, M ^{[1
]}

Stojakovic, G ^{[1
]}

Robl, W ^{[1
]}

Gluschenkov, O ^{[1
]}

Liegl, B ^{[1
]}

Wu, CH ^{[1
]}

Wu, Q ^{[1
]}

Li, WK ^{[1
]}

Choi, CJ ^{[1
]}

Arnold, N ^{[1
]}

Joseph, T ^{[1
]}

Varn, K ^{[1
]}

Weybright, M ^{[1
]}

McStay, K ^{[1
]}

Kang, WT ^{[1
]}

Li, Y ^{[1
]}

Bukofsky, S ^{[1
]}

Jammy, R ^{[1
]}

Schutz, R ^{[1
]}

Gutmann, A ^{[1
]}

Bergner, W ^{[1
]}

Divakaruni, R ^{[1
]}

Back, D ^{[1
]}

Crabbe, E ^{[1
]}

Mueller, W ^{[1
]}

机构：

[1] IBM Corp, Microelect, Semicond R&D Ctr, Hopewell Jct, NY 12533 USA

来源：

2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIT.2002.1015384

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a 110 nm half-pitch DRAM technology utilizing an 8F(2) vertical transistor trench cell and optimized for ease of manufacturing and scaling. All four critical lithography steps are regular patterns in the array. High performance is provided through the use of tungsten Word-Lines, tungsten Bit-Lines, arid the double-gated vertical array transistors. Area enhancement techniques in the trench capacitor allow the use of conventional dielectric materials into the 110 nm generation. A 512Mb prototype chip has been fabricated using this technology.

引用

页码：52 / 53

页数：2

共 7 条

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