Sources of line-width roughness for EUV resists

被引：27

作者：

Cao, HB ^{[1
]}

Yueh, W ^{[1
]}

Rice, BJ ^{[1
]}

Roberts, J ^{[1
]}

Bacuita, T ^{[1
]}

Chandhok, M ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XXI, PTS 1 AND 2 | 2004年 / 5376卷

关键词：

D O I：

10.1117/12.536041

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Resists for the next generation of lithography must be able to meet stringent line width roughness (LWR) targets. The LWR requirements, governed by device performance, are the same regardless of the lithographic technology that is chosen. Unfortunately no resist platform for any technology (EUV, 157 nm, 193 nm) is on track to meet the targets for the 45 nm and the 32 nm technology nodes. In order to understand the fundamental sources of LWR, we designed an experiment to statistically vary resist parameters for EUV resists. The results of this study show methods to improve LWR and shed light on the sources of LWR.

引用

页码：757 / 764

页数：8