Self-Tuning PLL: A New, Easy, Fast and Highly Efficient Phase-Locked Loop Algorithm

A phase-locked loop or phase lock loop (PLL) is, essentially, a closed loop control system, where its output signal (regulated) maintains a direct (chosen) relationship to the input signal (unregulated). If the phases of the input and output signals remain the same, their frequencies will also match. In its usual way, a PLL is an electronic circuit with filters and controllers that must be tuned each time, according to the input signal parameters. As a contribution and novelty, this paper introduces a new, easy, fast and highly efficient PLL algorithm, that it does not need to adjust every time the input signal changes. This makes it independent of the input signal it receives and, therefore, and in a certain way, universally applicable. In addition, the proposal is implemented exclusively by software, housed in a microcontroller, which also represents another novelty. As another remarkable feature, the proposed algorithm is very simple, with a very low computational cost, which makes it very stable, practically insensitive to noise, and very fast. These characteristics and the performance shown over a wide range of input signal frequencies, make the proposed algorithm suitable for use in different applications, from the electricity grid synchronization to the demodulation of frequency modulation, DC motor drives, etc. In addition to frequency and phase tracking, the developed algorithm generates the signal corresponding to the fundamental frequency of the input signal. Furthermore, the algorithm behavior is not affected by the input signal distortion and is independent of its initial phase. The performance and excellent behavior of the developed algorithm are evaluated through simulations and experimental tests.