Montgomery's multiplication technique: How to make it smaller and faster

被引:0
作者
Walter, CD [1 ]
机构
[1] Univ Manchester, Inst Sci & Technol, Dept Computat, Manchester M60 1QD, Lancs, England
来源
CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS | 1999年 / 1717卷
关键词
computer arithmetic; cryptography; RSA; Montgomery modular multiplication; higher radix methods; systolic arrays; testing; error correction; fault tolerance; checker function; differential pourer analysis; DPA;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Montgomery's modular multiplication algorithm has enabled considerable progress to be made in the speeding up of RSA cryptosystems. Perhaps the systolic array implementation stands out most in the history of its success. This article gives a brief history of its implementation in hardware, taking a broad view of the many aspects which need to be considered in chip design. Among these are trade-offs between area and time, higher radix methods, communications both within the circuitry and with the rest of the world, and, as the technology shrinks, testing, fault tolerance, checker functions and error correction. We conclude that a linear, pipelined implementation of the algorithm may be part of best policy in thwarting differential power attacks against RSA.
引用
收藏
页码:80 / 93
页数:14
相关论文
共 29 条
  • [1] Montgomery modular exponentiation on reconfigurable hardware
    Blum, T
    Paar, C
    [J]. 14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 1999, : 70 - 77
  • [2] Boneh Dan, 1997, LECT NOTES COMPUTER, V1233, P37, DOI DOI 10.1007/3-540-69053-0_
  • [3] A REGULAR LAYOUT FOR PARALLEL ADDERS
    BRENT, RP
    KUNG, HT
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1982, 31 (03) : 260 - 264
  • [4] THE AREA-TIME COMPLEXITY OF BINARY MULTIPLICATION
    BRENT, RP
    KUNG, HT
    [J]. JOURNAL OF THE ACM, 1981, 28 (03) : 521 - 534
  • [5] Brickell E. F., 1983, Advances in Cryptology, Proceedings of Crypto 82, P51
  • [6] HARDWARE IMPLEMENTATION OF MONTGOMERY MODULAR MULTIPLICATION ALGORITHM
    ELDRIDGE, SE
    WALTER, CD
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1993, 42 (06) : 693 - 699
  • [7] A FASTER MODULAR MULTIPLICATION ALGORITHM
    ELDRIDGE, SE
    [J]. INTERNATIONAL JOURNAL OF COMPUTER MATHEMATICS, 1991, 40 (1-2) : 63 - 68
  • [8] Floating-point unit in standard cell design with 116 bit wide dataflow
    Gerwig, G
    Kroener, M
    [J]. 14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 1999, : 266 - 273
  • [9] Knuth D.E., 1981, ART COMPUTER PROGRAM, V2, P441
  • [10] KOBLITZ N, 1987, GRADUATE TEXTS MATH, V114