Decreasing the Off-current for Vertical TFT by Using an Insulating Layer between Source and Drain

被引：3

作者：

Zhang, P. ^{[1
]}

Jaques, E. ^{[1
]}

Rogel, R. ^{[1
]}

Bonnaud, O. ^{[1
]}

机构：

[1] Univ Rennes 1, UMR 6164, Dept Microelect & Microcapteurs, Inst Elect & Telecommun Rennes, F-35042 Rennes, France

来源：

THIN FILM TRANSISTORS 11 (TFT 11) | 2012年 / 50卷 / 08期

关键词：

THIN-FILM-TRANSISTOR; POLYCRYSTALLINE SILICON; LOW-PRESSURE; TECHNOLOGY; CRYSTALLIZATION;

D O I：

10.1149/05008.0059ecst

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

A novel polysilicon vertical thin film transistor (VTFT) has been fabricated based on a low-temperature (T <= 600 degrees C) process. This new structure eliminates the large overlapping area between source and drain, and thus reduced the off-current and increased the I-on/I-off ratio. The technologically key point lies in the introduction of an insulating layer between source and drain, and the electrical properties of the fabricated VTFTs using different insulating layers are compared. These first results highlight that the SiO2 insulating layer shows great advantages over the Si3N4 insulating layer. The reduced off-current has revealed some potential applications for high density integration and high drive current.

引用

页码：59 / 64

页数：6

共 11 条

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