Power analysis of VLSI interconnect with RLC tree models and model reduction

被引：1

作者：

Shin, Youngsoo ^{[1
]}

Lee, Junghyup ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2006年 / 15卷 / 03期

关键词：

low power; interconnect; model reduction; CMOS;

D O I：

10.1142/S0218126606003180

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The lumped capacitance model, which ignores the existence of wire resistance, has been traditionally used to estimate the charging and discharging power consumption of CMOS circuits. We show that this model is not correct by pointing out that MOSFETs consume only part of the energy supplied by the source. During this study, it was revealed that about 20% of the power is consumed in the wire resistance of the buffered global interconnect, when the interconnect is modeled with RC tree networks. The percentage goes up to 30 when RLC model is used indicating the importance of inductance in interconnect model for power estimation. For RLC networks, we propose a compact yet very accurate power estimation method based on a model reduction technique.

引用

页码：399 / 408

页数：10

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