Synthesis of analog CMOS circuits

In this paper we describe an efficient method for transistor sizing in cell level analog circuits. An equation based method is used. SPICE quality device models are used and the sizing problem is posed as an optimisation problem. KCL, KVL and matching constraints are taken into account in the formulation of the optimisation problem without explicitly introducing them as constraints as was done previously. A tool developed based on th is method has been used to synthesise and study performance trade-offs in various CMOS op amps.