Effective Task Scheduling and IP Mapping Algorithm for Heterogeneous NoC-Based MPSoC

被引:9
作者
Yang, Peng-Fei [1 ]
Wang, Quan [1 ]
机构
[1] Xidian Univ, Sch Comp, Xian 710071, Peoples R China
关键词
EVOLUTIONARY ALGORITHM;
D O I
10.1155/2014/202748
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Quality of task scheduling is critical to define the network communication efficiency and the performance of the entire NoC-(Network-on-Chip-) based MPSoC (multiprocessor System-on-Chip). In this paper, the NoC-based MPSoC design process is favorably divided into two steps, that is, scheduling subtasks to processing elements (PEs) of appropriate type and quantity and then mapping these PEs onto the switching nodes of NoC topology. When the task model is improved so that it reflects better the real intertask relations, optimized particle swarm optimization (PSO) is utilized to achieve the first step with expected less task running and transfer cost as well as the least task execution time. By referring to the topology of NoC and the resultant communication diagram of the first step, the second step is done with the minimal expected network transmission delay as well as less resource consumption and even power consumption. The comparative experiments have shown the preferable resource and power consumption of the algorithm when it is actually adopted in a system design.
引用
收藏
页数:8
相关论文
共 27 条
[1]   Task assignment for Heterogeneous Multiprocessors using Re-Excited Particle Swarm Optimization [J].
Abdelhalim, M. B. .
ICCEE 2008: PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON COMPUTER AND ELECTRICAL ENGINEERING, 2008, :23-27
[2]  
Addo-Quaye C., 2005, P IEEE INT SOC C, P25
[3]  
Agyeman M. O., 2011, Proceedings 2011 6th International Symposium on Parallel Computing in Electrical Engineering (PARELEC 2011), P25, DOI 10.1109/PARELEC.2011.40
[4]  
Ahmad I., 1994, Proceedings of the 1994 International Conference on Parallel Processing, P47
[5]  
Arnold Oliver, 2010, Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2010), P110, DOI 10.1109/ICSAMOS.2010.5642075
[6]   Run-Time Task Allocation Considering User Behavior in Embedded Multiprocessor Networks-on-Chip [J].
Chou, Chen-Ling ;
Marculescu, Radu .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (01) :78-91
[7]  
Daoud M. I., 2006, INT C PAR DISTR SYST, V1, P11
[8]  
De Micheli G., 2006, NETWORKS CHIPS TECHN
[9]   Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems [J].
Ferrandi, Fabrizio ;
Lanzi, Pier Luca ;
Pilato, Christian ;
Sciuto, Donatella ;
Tumeo, Antonino .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (06) :911-924
[10]  
Ganeshpure Kunal, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI. Emerging VLSI Technologies and Architectures (ISVLSI), P171, DOI 10.1109/ISVLSI.2013.6654654