Implementation of image copyright protection tool using hardware-software co-simulation

被引：2

作者：

Sinha Roy, Subhrajit ^{[1
,2
]}

Basu, Abhishek ^{[1
]}

Chattopadhyay, Avik ^{[2
]}

Das, Tirtha Sankar ^{[3
]}

机构：

[1] RCC Inst Informat Technol, Elect & Commun Engn, South Canal Rd, Kolkata 700015, India

[2] Univ Calcutta, Radio Phys & Elect, 92 Acharya Prafulla Chandra Rd, Kolkata 700009, India

[3] Ramakrishna Mahato Govt Engn Coll, Elect & Commun Engn, Purilia, W Bengal, India

来源：

MULTIMEDIA TOOLS AND APPLICATIONS | 2021年 / 80卷 / 03期

关键词：

Digital watermarking; FPGA implementation; Hardware-software co-simulation; LSB matching; Spatial domain; Visual information hiding; DATA HIDING SCHEME; WATERMARKING ALGORITHM; DIGITAL IMAGES; SYSTEM; FPGA; STEGANALYSIS; ARCHITECTURE; DESIGN; DSP;

D O I：

10.1007/s11042-020-09944-w

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The proposed work presents particulars of a technique for the design and hardware implementation of an information hiding scheme using hardware-software co-simulation. The methodology aims to improve the design verification efficiency, development time and cost for DSP solutions. The scheme represents architecture for visual information hiding framework where information bits embedded into the host image by means of LSB matching technique. The design is tested by targeting a Spartan-3A DSP edition board (XC3SD3400A-4FGG676C) and the simulated results illustrate that this architecture provides a better opening for application specific events as well as explores different areas concerned to low cost hardware implementation through a graphical user interface.

引用

页码：4263 / 4277

页数：15

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