A Test Structure for Assessing Individual Contact Resistance

被引：3

作者：

Liu, Frank ^{[1
]}

Agarwal, Kanak ^{[1
]}

机构：

[1] IBM Austin Res Lab, Austin, TX 78758 USA

来源：

ICMTS 2009: 2009 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES | 2009年

关键词：

D O I：

10.1109/ICMTS.2009.4814641

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Accurate measurement of contact resistance is crucial for advanced nanometer CMOS processes. An equally important requirement is to measure contact resistances in the same micro-environment as the device-undertest (DUT) will be used in real designs. With complicated interactions among various layout shapes in nanometer CMOS processes, test structures with adequate scalability is needed. In this paper we present a scalable contact resistance measurement structure, which can accommodate tens of thousands of DUTs. The measurement results from a 65nm CMOS technology are also presented.

引用

页码：201 / 204

页数：4

共 4 条

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Kasai, N
Koga, H
Takaishi, Y
[J]. ICMTS 2001: PROCEEDINGS OF THE 2001 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 2001, : 177 - 181
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