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- [21] A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and <-255-dB FOMjitter PROCEEDINGS OF THE 37TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, VLSID 2024 AND 23RD INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, ES 2024, 2024, : 156 - 161
- [25] 1 kHz, 10 mJ, sub-200 fs regenerative amplifier utilizing a dual-crystal configuration of Yb:CaGdAlO4 featuring exceptional beam quality OPTICS EXPRESS, 2024, 32 (20): : 34408 - 34416
- [26] A Class-C Injection-Locked Tripler with 48 dB Sub-Harmonic Suppression and 15 fs Additive RMS Jitter in 0.13μm BiCMOS Process 2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, : 2740 - 2744
- [28] A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology ESSCIRC 2022- IEEE 48TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), 2022, : 237 - 240
- [30] A 0.2-to-39.2GHz 66.2-fs Jitter and-71.3dBc Spur Sub-Sampling PLL Using DAC-Based Constant Control Voltage Compensator and Quad-Mode 2nd Harmonic Filtering Oscillator 2024 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, RFIC 2024, 2024, : 215 - 218