Transmission gate-based 9T SRAM cell for variation resilient low power and reliable internet of things applications

Higher variation resilience, lower power consumption, and higher reliability are the three principal design metrics for designing a static random-access memory (SRAM) cell. The most intuitive way to achieve lower power consumption is voltage scaling. However, voltage scaling at nanometre technology nodes leads to degradation in the robustness of the SRAM cell and decreased data stability. It is proved that conventional 6T SRAM fails to maintain its stability in scaled technology, particularly in the deep-subthreshold regime. Furthermore, SRAM cells utilising techniques such as read decoupling, for achieving reliable read operation, tend to increase leakage current resulting in higher hold power, which contributes a major portion to the total power consumption in modern internet of things devices. To cater to the requirements of higher robustness and lower hold power dissipation, a transmission gate-based 9T SRAM is proposed, which achieves these requirements at the cost of slightly higher read and write access time. The simulations are performed utilising a 16-nm complementary metal oxide semiconductor model.