Suppression of leakage current in carbon nanotube field-effect transistors

Carbon nanotube field-effect transistor (CNT FET) has been considered as a promising candidate for future high-performance and low-power integrated circuits (ICs) applications owing to its ballistic transport and excellent immunity to short channel effects (SCEs). Still, it easily suffers from the ambipolar property, and severe leakage current at off-state originated from gate-induced drain leakage (GIDL) in CNT FETs with small bandgap. Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs, there is still a lack of the structure with excellent scalability, which will hamper the development of CNT FETs toward a competitive technology node. Here, we explore how the device geometry design affects the leakage current in CNT FETs, and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional (2D) TCAD simulations. Among all the proposed structures, the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process. According to the simulation results, the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/mu m and an on-current as high as about 2.1 mA/mu m at a supply voltage of -1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs.