Evaluation of Intrinsic Parameter Fluctuations on 45, 32 and 22nm Technology Node LP N-MOSFETs

被引：7

作者：

Cheng, B. ^{[1
]}

Roy, S. ^{[1
]}

Brown, A. R. ^{[1
]}

Millar, C. ^{[1
]}

Asenov, A. ^{[1
]}

机构：

[1] Univ Glasgow, Dept Elect & Elect Engn, Glasgow G12 8QQ, Lanark, Scotland

来源：

ESSDERC 2008: PROCEEDINGS OF THE 38TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2008年

关键词：

D O I：

10.1109/ESSDERC.2008.4681695

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The quantitative evaluation of the impact of key sources of statistical variability (SV) are presented for LP nMOSFETs corresponding to 45nm, 32nm and 22nm technology generation transistors with bulk, thin body (TB) SOI and double gate (DG) device architectures respectively. The simulation results indicate that TBSOI and DG are not only resistant to random dopant induced variability, but also are more tolerant to line edge roughness induced variability. Even two technology generations ahead from their bulk counterparts, DG MOSFETs will still have 4 times less variability than bulk devices.

引用

页码：47 / 50

页数：4

共 11 条

[1] Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs [J].

Asenov, A ;

Brown, AR ;

Davies, JH ;

Kaya, S ;

Slavcheva, G .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (09) :1837-1852

[2] Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness [J].

Asenov, A ;

Kaya, S ;

Brown, AR .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (05) :1254-1260

[3] Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: A 3-D density-gradient simulation study [J].

Asenov, A ;

Slavcheva, G ;

Brown, AR ;

Davies, JH ;

Saini, S .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (04) :722-729

[4] Simulation of statistical variability in nano MOSFETs [J].

Asenov, Asen .

2007 Symposium on VLSI Technology, Digest of Technical Papers, 2007, :86-87

[5] Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture [J].

Brown, Andrew R. ;

Roy, Gareth ;

Asenov, Asen .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (11) :3056-3063

[6] Intrinsic parameter fluctuations in nanometre scale thin-body SOI devices introduced by interface roughness [J].

Brown, AR ;

Adamu-Lema, F ;

Asenov, A .

SUPERLATTICES AND MICROSTRUCTURES, 2003, 34 (3-6) :283-291

[7]

CATHIGNOL A, IEEE ELECT IN PRESS

[8] Bipolar quantum corrections in resolving individual dopants in 'atomistic' device simulation [J].

Roy, G ;

Brown, AR ;

Asenov, A ;

Roy, S .

SUPERLATTICES AND MICROSTRUCTURES, 2003, 34 (3-6) :327-334

[9] Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs [J].

Roy, Gareth ;

Brown, Andrew R. ;

Adamu-Lema, Fikru ;

Roy, Scott ;

Asenov, Asen .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (12) :3063-3070

[10] Line edge roughness characterization with a three-dimensional atomic force microscope: Transfer during gate patterning processes [J].

Thiault, J ;

Foucher, J ;

Tortai, JH ;

Joubert, O ;

Landis, S ;

Pauliac, S .

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2005, 23 (06) :3075-3079

← 1 2 →