Toward Speculative Loop Pipelining for High-Level Synthesis

被引：15

作者：

Derrien, Steven ^{[1
]}

Marty, Thibaut ^{[1
]}

Rokicki, Simon ^{[1
]}

Yuki, Tomofumi ^{[1
]}

机构：

[1] Univ Rennes, CNRS, INRIA, IRISA, F-35000 Rennes, France

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2020年 / 39卷 / 11期

关键词：

Accelerator architectures; automatic parallelization; high level synthesis; high-level-synthesis; pipelined circuits;

D O I：

10.1109/TCAD.2020.3012866

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Loop pipelining (LP) is a key optimization in modern high-level synthesis (HLS) tools for synthesizing efficient hardware datapaths. Existing techniques for automatic LP are limited by static analysis that cannot precisely analyze loops with data-dependent control flow and/or memory accesses. We propose a technique for speculative LP that handles both control-flow and memory speculations in a unified manner. Our approach is entirely expressed at the source level, allowing a seamless integration to development flows using HLS. Our evaluation shows significant improvement in throughput over standard LP.

引用

页码：4229 / 4239

页数：11

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