Design considerations for integrated CMOS reflective-type phase shifters

An analysis of reflective-type phase shifters with transformed single-resonant loads for integrated CMOS phased-array implementations is presented. Several components of the standard lumped-element coupler can be eliminated without significant performance degradation, to allow more compact implementations. It is found that the varactor should be chosen as small as feasible to minimize sensitivity to parasitic resistance. Larger varactors reduce sensitivity to parasitic capacitance, but this can be compensated for in the phase shifter design. A general design procedure for reflective-type phase shifters is given. A phase shifter operating at 2.0 GHz has been designed and implemented in a 0.18 mu m CMOS process using the design procedures outlined, and it occupies an area of 0.75 mm(2) and consumes 6.8 mW of power. The measured phase shift range is 308 degrees for a control voltage varying from 0-1.8 V, which to our knowledge is the largest phase shift range of any CMOS reflective-type phase shifter reported to date.