The Impact of Holding Voltage of Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System With CMOS ICs Under System-Level ESD and EFT/Burst Tests

被引：10

作者：

Shen, Yu-Shu ^{[1
]}

Ker, Ming-Dou ^{[1
]}

机构：

[1] Natl Yang Ming Chiao Tung Univ, Inst Elect, Hsinchu, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2021年 / 68卷 / 05期

关键词：

Electrical fast transient (EFT)/burst test; holding voltage; signal integrity; system-level electrostatic discharge (ESD); transient voltage suppressor (TVS);

D O I：

10.1109/TED.2021.3063208

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Transient voltage suppressor (TVS) has been widely used on the printed circuit board (PCB) to protect the microelectronics system against the system-level electrostatic discharge (ESD) and electrical fast transient/burst (EFT/B) events. However, the signal integrity of the system operationsmay be destroyedafter the system-levelESD and EFT/B immunity test, if the TVSwere designedwith a holding voltage of lower than the operating voltage of the CMOS ICs equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different holding voltages was studied under the system- level ESD and EFT/B immunity test. By monitoring the transient voltage waveforms in the time domain during system- level ESD and EFT/B immunity test, the system malfunction has been found when the TVS is with a lower holding voltage. Therefore, the holding voltage of the TVS must be greater than the system operating voltage to maintain the signal integrity in the field applications.

引用

页码：2152 / 2159

页数：8

共 11 条

[1]

[Anonymous], 2001, 610004 IEC

[2]

[Anonymous], 2001, STM51 ESD

[3]

[Anonymous], 2004, 610004 IEC

[4]

ASHTON RA, 1995, ICMTS 1995 - PROCEEDINGS OF THE 1995 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, P127, DOI 10.1109/ICMTS.1995.513959

[5] Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions [J].

Fan, Jun ;

Ye, Xiaoning ;

Kim, Jingook ;

Archambeault, Bruce ;

Orlandi, Antonio .

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2010, 52 (02) :392-400

[6] How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on [J].

Ker, MD ;

Chang, HH .

JOURNAL OF ELECTROSTATICS, 1999, 47 (04) :215-248

[7] Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations [J].

Ker, Ming-Dou ;

Hsu, Sheng-Fu .

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2006, 6 (03) :461-472

[8] ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test [J].

Ker, Ming-Dou ;

Chiu, Po-Yen ;

Shieh, Wuu-Trong ;

Wang, Chun-Chi .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (02) :642-645

[9] An improved transmission line pulsing (TLP) setup for electrostatic discharge (ESD) testing in semiconductor devices and ICs [J].

Lee, JC ;

Young, R ;

Liou, JJ ;

Croft, GD ;

Bernier, JC .

ICMTS 2001: PROCEEDINGS OF THE 2001 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 2001, :233-238

[10]

Shen Y.-S., 2020, P IEEE INT S PHYS FA, P424

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