SAR ADC Algorithm with Redundancy

被引:40
作者
Ogawa, Tomohiko [1 ]
Kobayashi, Haruo [1 ]
Hotta, Masao [2 ]
Takahashi, Yosuke [1 ]
San, Hao [1 ]
Takai, Nobukazu [1 ]
机构
[1] Gunma Univ, Dept Elect Engn, Gunma, Japan
[2] Musashi Inst Technol, Dept Informat Network Engn, Musashino, Tokyo, Japan
来源
2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 | 2008年
关键词
SAR ADC; Digital Error Correction; Non-binary; Redundancy;
D O I
10.1109/APCCAS.2008.4746011
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper describes a redundant algorithm for a highly reliable Successive Approximation Register (SAR) ADC where mistakes of comparator decision can be digitally-corrected. We generalize a conventional non-binary search algorithm which requires more conversion steps in the SAR ADC than the binary search algorithm, and clarify which decision errors can be digitally-corrected with the derived redundant algorithm. We also shows that the sampling speed of the SAR ADC using the proposed algorithm can be faster when the incomplete settling effects of the DAC inside the SAR ADC are taken into account.
引用
收藏
页码:268 / +
页数:3
相关论文
共 5 条
[1]  
HESENER M, 2007, ISSCC FEB
[2]  
HOTTA M, 2006, IEEJ INT AN VLSI WOR
[3]  
*ISSCC, 2005, ISSCC SHORT COURS AU
[4]  
KUTTNER F, 2002, ISSCC FEB
[5]  
SHIMOKURA S, 2007, IEEJ INT AN VLSI WOR