Co-design of DNN Model Optimization for Binary ReRAM Array In-memory Processing

被引:2
作者
Guan, Yue [1 ]
Ohsawa, Takashi [1 ]
机构
[1] Waseda Univ, Grad Sch Informat Prod & Syst, Kitakyushu, Fukuoka, Japan
来源
2019 IEEE 11TH INTERNATIONAL MEMORY WORKSHOP (IMW 2019) | 2019年
关键词
neuromorphic ReRAM; binary neural network; fabrication fluctuation;
D O I
10.1109/imw.2019.8739722
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, a novel design of ReRAM neuromorphic system is proposed to process deep neural network ( DNN) fully in array efficiently. A binary neural network model is constructed and optimized on MNIST dataset. The obtained model is simulated to be processed with the proposed ReRAM array. Co-design between hardware and network model optimization in software is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.
引用
收藏
页码:32 / 35
页数:4
相关论文
共 10 条
[1]  
Chen LR, 2017, DES AUT TEST EUROPE, P19, DOI 10.23919/DATE.2017.7926952
[2]  
Chen WH, 2018, ISSCC DIG TECH PAP I, P494, DOI 10.1109/ISSCC.2018.8310400
[3]  
Courbariaux M., 2016, ARXIV160202830
[4]  
Kamiyanagi M, 2011, IEICE T ELECTRON, VE94C, P760, DOI [10.1587/transele.E94.C.760, 10.1587/transele.E94.C760]
[5]   A UNIFIED SYSTOLIC ARCHITECTURE FOR ARTIFICIAL NEURAL NETWORKS [J].
KUNG, SY ;
HWANG, JN .
JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 1989, 6 (02) :358-387
[6]  
Li B., 2014, 2014 Design, Automation Test in Europe Conference Exhibition (DATE), P1
[7]   A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks [J].
Mittal, Sparsh .
MACHINE LEARNING AND KNOWLEDGE EXTRACTION, 2019, 1 (01) :75-114
[8]  
Ni Leibin., 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), P1
[9]   XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks [J].
Rastegari, Mohammad ;
Ordonez, Vicente ;
Redmon, Joseph ;
Farhadi, Ali .
COMPUTER VISION - ECCV 2016, PT IV, 2016, 9908 :525-542
[10]   Efficient Processing of Deep Neural Networks: A Tutorial and Survey [J].
Sze, Vivienne ;
Chen, Yu-Hsin ;
Yang, Tien-Ju ;
Emer, Joel S. .
PROCEEDINGS OF THE IEEE, 2017, 105 (12) :2295-2329