Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis

Early exploration of communication architectures and timing behaviors is a key step in modern system design flows. This paper proposes a framework for the design space exploration of DSP applications. The proposed approach is based on four main abstraction levels: algorithmic, architectural (communication interface), behavioral (I/O timing diagram) and RTL. The system specification is based on a set of Behavioral Description Models (BDM) which communicate through channels: each BDM represents a hardware component. For this purpose, a BDM (1) embeds a sequential function-that describes the computing algorithm to be implemented-into a module and (2) includes a set of I/O and control processes. Communication architectures and timing behaviors (I/O scheduling, I/O parallelism ...) of each BDM can be modified and easily explored by adding I/O and control code into the dedicated concurrent processes. This allows keeping the description of the functionality unchanged throughout the refinement steps. The high-level synthesis tool GAUT is next used to generate, from the unmodified sequential function, the RTL architectures that respect the constraints i.e. the refined I/O timing behavior. The use of BDMs for the system description allows the designer to simulate and to evaluate several communication architectures and several timing behaviors during the performance analysis phase. The interest of our approach is shown through the case study of a Hyper-plane Intersection and Selection HIS algorithm for MC-CDMA system.