Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays

Memristors have shown significant promise in recent times both in logic synthesis and memory-subsystem design. A 2D-crossbar architecture built with memristor arrays provides a convenient platform for storing multi-valued memory states by utilizing the analog variation of current-induced resistance through these cells. The integration of CMOS components and non-CMOS memristor cells further enhances the scope of their applications to various complex system design. However, present-day memristor cells, by virtue of their inherent structural constructs, are prone to various manufacturing defects and sensitive to operational modalities. Therefore, robust and fast testing methods are frequently needed to ensure the correctness of their functionality. Existing techniques for testing memristor arrays are either ad-hoc in nature or suited for application-specific designs, and no attempt has been made to optimize test-time. In this work, we present a graph-based technique to select some sneak-paths and sensitize these to generate test-vectors for a 2D memristor-array. The proposed method relies on Eulerian graph traversal and matching in bipartite graphs to produce tests for detecting stuck-at, slow-to-write, and deep faults in all memristor-cells. Simulation results with LTspice demonstrate the effectiveness and superiority of the proposed method to prior art in terms of test time and fault-coverage.