FPGA Implementation of Fractional-Order Chua's Chaotic System

被引：0

作者：

Abd El-Maksoud, Ahmed J. ^{[1
]}

Abd El-Kader, Ayman A. ^{[1
]}

Hassan, Bahy G. ^{[1
]}

Abdelhamed, Mohamed A. ^{[1
]}

Rihan, Nader G. ^{[1
]}

Tolba, Mohamed F. ^{[2
]}

Said, Lobna A. ^{[2
]}

Radwan, Ahmed G. ^{[2
,3
]}

Abu-Elyazeed, Mohamed F. ^{[1
]}

机构：

[1] Cairo Univ, Elect & Comm Eng Dept, Giza, Egypt

[2] Nile Univ, NISC Res Ctr, Cairo, Egypt

[3] Cairo Univ, Dept Engn Math & Phys, Giza, Egypt

来源：

2018 7TH INTERNATIONAL CONFERENCE ON MODERN CIRCUITS AND SYSTEMS TECHNOLOGIES (MOCAST) | 2018年

关键词：

Fractional calculus; Chaos; Chua's circuit; FPGA;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper introduces FPGA implementation of fractional order double scrolls chaotic system based on Chua circuit. Grunwald-Letnikov's (GL) definition is used to generalize the chaotic system equations into the fractional-order domain. Xilinx ISE 14.5 is used to simulate the proposed design and Artix-7 XC7A100T FPGA is used for system realization. Experimental results are presented on digital oscilloscope and the error between theoretical and experimental results is calculated. Also, various interesting attractors are obtained with respect to different parameters values and window sizes. Some techniques have been employed to increase the throughput to 7.685 Gbit/Sec with 96-bits overall output.

引用

页数：4

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