A calibrated phase/frequency detector for reference spur reduction in charge-pump PLLs

被引:38
作者
Charles, Cameron T. [1 ]
Allstot, David J. [1 ]
机构
[1] Univ Washington, Dept Elect Engn, Seattle, WA 98195 USA
来源
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2006年 / 53卷 / 09期
关键词
phase/frequency detector (PFD); phase-locked loop (PLL); voltage control oscillator (VCO);
D O I
10.1109/TCSII.2006.880030
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This brief presents a new technique for minimizing reference spurs in a charge-pump phase-locked loop (PLL) while maintaining dead-zone-free operation. The proposed circuitry uses a phase/frequency detector with a variable delay element in its reset path, with the delay length controlled by feedback from the charge-pump. Simulations have been performed with several PLLs to compare the proposed circuitry with previously reported techniques. The proposed approach shows improvements over previously reported techniques of 12 and 16 dB in the two closest reference spurs.
引用
收藏
页码:822 / 826
页数:5
相关论文
共 7 条
[1]   CHARGE-PUMP PHASE-LOCK LOOPS [J].
GARDNER, FM .
IEEE TRANSACTIONS ON COMMUNICATIONS, 1980, 28 (11) :1849-1858
[2]  
JOHNS DA, 1997, ANALOG INTEGRATED CI
[3]   5-GHz CMOS wireless LANs [J].
Lee, TH ;
Samavati, H ;
Rategh, HR .
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2002, 50 (01) :268-280
[4]   Low-jitter process-independent DLL and PLL based on self-biased techniques [J].
Maneatis, JG .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (11) :1723-1732
[5]  
PERROTT MH, 2002, PLL DESIGN USING PLL
[6]  
Razavi B, 2011, RF Microelectronics, V2nd
[7]  
RHEE W, 1999, P IEEE INT S CIRC SY, V2, P363