Frequency synthesizer for on-chip testing and automated tuning

被引：0

作者：

Valero-López, AY ^{[1
]}

Valdes-Garcia, A ^{[1
]}

Sánchez-Sinencio, E ^{[1
]}

机构：

[1] Texas A&M Univ, Analog & Mixed Signal Ctr, College Stn, TX 77843 USA

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a compact, phase-locked loop (PLL) based, frequency synthesizer suitable for built-in testing and automatic tuning applications operating in the 100MHz frequency range. Key features of this design include a differential charge pump with common mode feedback (CMFB) and a voltage controlled oscillator (VCO) based on a pseudo-differential OTA with a linear transconductance control and tuning invariant output resistance. Experimental results from an integrated prototype fabricated using standard 0.35mum CMOS technology are presented. The measured HD3 of the output signal is better than -39dB over 80% of the tuning range: 40-160MHz. The circuit occupies a silicon area of 200x100mum(2) and operates from a 3.3V power supply.

引用

页码：565 / 568

页数：4

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