A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

被引：40

作者：

Lee, Haechang ^{[1
]}

Chang, Kun-Yung Ken ^{[1
]}

Chun, Jung-Hoon ^{[1
]}

Wu, Ting ^{[1
]}

Frans, Yohan ^{[1
]}

Leibowitz, Brian ^{[1
]}

Nguyen, Nhat ^{[1
]}

Chin, T. J. ^{[1
]}

Kaviani, Kambiz ^{[1
]}

Shen, Jie ^{[1
]}

Shi, Xudong ^{[1
]}

Beyene, Wendemagegnehu T. ^{[1
]}

Li, Simon ^{[1
]}

Navid, Reza ^{[1
]}

Aleksic, Marko ^{[1
]}

Lee, Fred S. ^{[1
]}

Quan, Fredy

Zerbe, Jared ^{[1
]}

Perego, Rich ^{[1
]}

Assaderaghi, Fariborz ^{[1
]}

机构：

[1] Rambus Inc, Los Altos, CA 94022 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 04期

关键词：

CMOS memory integrated circuits; DRAM chips; equalizers; high-speed integrated circuits; interconnections; inter-symbol interference; jitter; synchronization; transceivers;

D O I：

10.1109/JSSC.2009.2014199

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a bidirectional, differential, 16 Gb/s per link memory interface that includes a Controller and an emulated DRAM physical interface (PHY) designed in 65 nm CMOS. To achieve high data rate, the interface employs the following technology ingredients: asymmetric equalization, asymmetric timing calibration, asymmetric link margining, inductor based (LC) PLLs, multi-phase error correction, and a data dependent regulator. At 16 Gb/s, this interface achieves a unit-interval to inverter FO4 ratio of 2.8 (Controller) and 1.4 (DRAM) and operates in a channel with 15 dB loss at Nyquist. Under such bandwidth limitations on and off chip, the Controller and DRAM PHYs consume 13 mW/Gb/s and 8 mW/Gb/s, respectively. Using PRBS 2(11)-1, the link achieves a timing margin of 0.19 UI at a BER of 1e-12 for both read and write operations.

引用

页码：1235 / 1247

页数：13

共 13 条

[1] Replica compensated linear regulators for supply-regulated phase-locked loops [J].

Alon, E ;

Kim, J ;

Pamarti, S ;

Chang, K ;

Horowitz, M .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (02) :413-424

[2] Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13μm CMOS [J].

Balamurugan, G ;

Jaussi, J ;

Johnson, DR ;

Casper, B ;

Martin, A ;

Kennedy, J ;

Mooney, R ;

Shanbhag, N .

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :356-359

[3]

CHANDRAKASAN A, 2001, DESIGN HIGH PERFORMA, P402

[4] A 16Gb/s/link, 64Gb/s bidirectional asymmetric memory interface cell [J].

Chang, Ken ;

Lee, Haechang ;

Chun, Jung-Hoon ;

Wu, Ting ;

Chin, T. J. ;

Kaviani, Kambiz ;

Shen, Jie ;

Shi, Xudong ;

Beyene, Wendem ;

Frans, Yohan ;

Leibowitz, Brian ;

Nguyen, Nhat ;

Quan, Fredy ;

Zerbe, Jared ;

Perego, Rich ;

Assaderaghi, Fari .

2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2008, :126-127

[5]

Chang TMS, 1998, TISS ENG, P216

[6]

Chaudhuri S, 2006, ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, P21

[7] 0.622-8.OGbps 150mW serial 10 macrocell with fully flexible preemphasis and equalization [J].

Farjad-Rad, R ;

Ng, HT ;

Lee, MJE ;

Senthinathan, R ;

Dally, WJ ;

Nguyen, A ;

Rathi, R ;

Poulton, J ;

Edmondson, J ;

Tran, J ;

Yazdanmehr, H .

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, :63-66

[8] A high-efficiency CMOS voltage doubler [J].

Favrat, P ;

Deval, P ;

Declercq, MJ .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (03) :410-416

[9] A 16-Gb/s differential I/O cell with 380fs RJ in an emulated 40nm DRAM process [J].

Nguyen, Nhat ;

Frans, Yohan ;

Leibowitz, Brian ;

Li, Simon ;

Navid, Reza ;

Aleksic, Marko ;

Lee, Fred ;

Quan, Fredy ;

Zerbe, Jared ;

Perego, Rich ;

Assaderaghi, Fari .

2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2008, :128-129

[10]

PEREGO R, 2007, RAMBUS DEV FORUM JAP

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