Power Integrity Chip-Package-PCB Co-Simulation for I/O Interface of DDR3 High-Speed Memory

被引：3

作者：

Chuang, Hao-Hsiang ^{[1
,2
]}

Wu, Shu-Jung ^{[1
,2
]}

Hong, Ming-Zhang

Hsu, Darren

Huang, Raphael

Hsiao, Li Chang

Wu, Tzong-Lin ^{[1
,2
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

[2] Nanya Technol Corp NTC, Taoyuan 33383, Taiwan

来源：

IEEE EDAPS: 2008 ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM | 2008年

关键词：

D O I：

10.1109/EDAPS.2008.4735991

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The modeling methodology of power distribution system (PDS) in three different levels, chip, package, and PCB for Input/Output (I/O) interface of DDR3 high-speed memory is established. The simulation results are verified with measurement results in frequency domain. Good agreement between them is clearly seen. The co-simulation with three kinds of PDS at the I/O interface and off-chip driver (OCD) circuits is constructed for time-domain simulation. The input impedance of three different PDSs is shown, and the simulation results for voltage variation and eye-patterns are compared with the corresponding input impedance. It is found lower input impedance have better power and signal integrity for the high-speed memory interface circuits. The PDS co-simulation of chip-package-PCB is important for the DDR3 circuit design.

引用

页码：31 / +

页数：3

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