Modified derivative superposition method for linearizing FET low noise amplifiers

被引：17

作者：

Aparin, V ^{[1
]}

Larson, LE ^{[1
]}

机构：

[1] QUALCOMM Inc, San Diego, CA 92121 USA

来源：

2004 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS | 2004年

关键词：

amplifier noise; intermodulation distortion; MOSFET amplifiers; nonlinearities; Volterra series;

D O I：

10.1109/RFIC.2004.1320540

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The degrading effect of the circuit reactances on the maximum IIP3 in the conventional derivative superposition (DS) method is explained using the Volterra series analysis. The effect of the subthreshold biasing of one of the FETs in the DS method on NF is also explained. A modified DS method is proposed to increase the Maximum IIP3 at RE It was used in a 0.25mum Si CMOS LNA designed for cellular CDMA receivers. The LNA achieved +17.2dBm IIP3 with 15.5dB gain, 1.6dB NF and 9mA @ 2.6V power consumption.

引用

页码：105 / 108

页数：4

共 6 条

[1]

APARIN V, 2004, UNPUB IEEE INT S CIR

[2]

Ding Y., 2001, IEEE INT SOL STAT CI, V22, P162

[3] A new linearization technique for MOSFET RF amplifier using multiple gated transistors [J].