Latchup Co-design Automation for HV Power Analog IC

被引：0

作者：

Fakhruddin, Mohammed ^{[1
]}

Vashchenko, Vladislav ^{[1
]}

机构：

[1] Analog Devices Inc, 160 Rio Robles, San Jose, CA 95134 USA

来源：

2022 44TH ANNUAL EOS/ESD SYMPOSIUM (EOS/ESD) | 2022年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

HV latchup co-design flow based on recently developed EDA tools is presented. The three-step flow targets HV latchup co-design of power analog IC's, enforces latchup rules, and analyzes sensitivity of the design to the injection current. Key strengths of the automated flow are the ability to identify and annotate injection and victim pockets, followed by area optimization through detection current estimation.

引用

页数：5

共 8 条

[1]

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[2]

Latchup Electronic Design Automation (EDA) EDA Tool Working Group., TR1800220 EDA ESD

[3] Dual Injection Latchup Phenomenon in HV Rail Based ESD Protection Networks [J].

Malobabic, Slavica ;

Marreiro, David ;

Vashchenko, Vladislav .

2019 41ST ANNUAL EOS/ESD SYMPOSIUM (EOS/ESD), 2019,

[4]

Marreiro D., 2018, 40 ELECT OVERSTRESSE

[5]

Marreiro D., 2019, 41 ANN EOSESD S

[6]

Mitchell T., 2017, 39 EOSESD S

[7]

Troutman R. R, 1986, LATCHUP CMOS TECHNOL, P165

[8]

Vashchenko V. A, 2018, EDN 0418

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