Signal integrity fault analysis using reduced-order modeling

被引：0

作者：

Attarha, A ^{[1
]}

Nourani, M ^{[1
]}

机构：

[1] Univ Texas, Ctr Integrated Circuits & Syst, Richardson, TX 75083 USA

来源：

39TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2002 | 2002年

关键词：

integrity fault; locality factor; reduced-order model; signal integrity; test pattern generation;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper aims at analysis of signal integrity, for the purpose of testing high speed interconnects. This requires taking into account the effect of inputs as well as parasitic RLC elements of the interconnect. To improve the analysis/simulation time in integrity fate It testing, we use reduced-order modeling that essentially Performs the analysis in the frequency domain. To demonstrate the generality, and usefulness of our method, we also discuss its application for test pattern generation targeting signal integrity loss.

引用

页码：367 / 370

页数：4

共 18 条

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