Hazard location and elimination in asynchronous circuits

被引：0

作者：

Wong, EMC ^{[1
]}

Gong, J ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Div Circuits & Syst, Singapore 639798, Singapore

来源：

ISIC-99: 8TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, DEVICES & SYSTEMS, PROCEEDINGS | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we introduce a novel efficient hazard location and elimination technique for asynchronous circuits implemented according to STG design style. We concern on analyzing gate-level circuits with uncertain component delays. This research work includes three parts: set up delay model test bench generation and hazard avoidance. VHDL is employed to write our simulation program.

引用

页码：347 / 350

页数：4

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