Design of a comparator in CMOS SOI

被引：5
|
作者：
Säll, E [1 ]
Vesterbacka, M [1 ]
机构：
[1] Linkoping Univ, Dept EE, SE-58183 Linkoping, Sweden
来源：
4TH IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS | 2004年
关键词：
D O I：
10.1109/IWSOC.2004.1319884
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper gives an introduction to the silicon-on-insulator (SOI) CMOS technology and presents the major advantages and disadvantages of using SOL It also presents the design of a comparator which has been sent for manufacturing, designed in a 0.13 mum partially depleted SOI CMOS process. The comparator is a first step towards the design of a complete 6-bit flash analog-to-digital converter with a sampling frequency of 1.5 GHz.
引用
收藏
页码：229 / 232
页数：4
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