This paper analyzes the step load response of a current-mode-controlled pulsewidth modulation (PWM) converter and also presents design guidelines for obtaining a good step load response. Analytical expressions for the step load response are derived in terms of the power stage and feedback compensation parameters. Control design to minimize the overshoot and settling time of the output voltage is presented. Analysis results are verified by large-signal simulations.
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页码:1115 / 1121
页数:7
相关论文
共 5 条
[1]
Harada K., 1981, PESC'81. IEEE Power Electronics Specialists Conference, P388
[2]
Lee F. C., 1980, PESC '80 Record. IEEE Power Electronics Specialists Conference, P284
机构:
Virginia Polytech Inst & State Univ, Bradley Dept Elect Engn, Virginia Power Elect Ctr, Blacksburg, VA 24061 USAVirginia Polytech Inst & State Univ, Bradley Dept Elect Engn, Virginia Power Elect Ctr, Blacksburg, VA 24061 USA
机构:
Virginia Polytech Inst & State Univ, Bradley Dept Elect Engn, Virginia Power Elect Ctr, Blacksburg, VA 24061 USAVirginia Polytech Inst & State Univ, Bradley Dept Elect Engn, Virginia Power Elect Ctr, Blacksburg, VA 24061 USA