Design of low noise avalanche photodiode single element detectors and linear arrays through CMOS process

Low noise silicon reach-through avalanche photodiodes are designed and implemented through 0.35 mu m high voltage CMOS process. Seperated absorption charge multiplication (SACM) structure with vertical n++/p+/pi/p four layers is adopted. The light sensitive area of two different size element detectors is 200 mu m and 500 mu m in diameter, respectively. Regardless of the size of the light sensitive area, the typical reach-through voltage and the breakdown voltage for both element detectors is tested to be 60 V, and 172 V, respectively. The distribution of the breakdown voltage across the wafer is like a superposition of two Gaussian distributions of one peak at 168 V corresponding to the fewer detectors close to the rim and the other at 172 V corresponding to the most detectors in the center. The temperature coefficient of the breakdown voltage is tested down to be 0.32 V/K. The dark current at the gain M=100 is tested to be 50 pA and 500 pA for each detector. The responsive wavelength is 400-1100 nm. The peak responsivity of the 500 mu m diameter detector is tested to be 57 A/W at 900 nm wavelength and with gain 100 to show the successful near infrared enhanced reponsivity. The excess noise factor is tested to be 34, much lower than those in the reported high voltage CMOS avalanche photodiodes. The yield is 100%. The devices are applied to a multiple-line Lidar to show the feasibility. Two 16x1 linear arrays of different pixel pitches are also designed and fabricated in the same way.