Plasticity mechanism for copper extrusion in through-silicon vias for three-dimensional interconnects

被引:48
作者
Jiang, Tengfei [1 ,2 ]
Wu, Chenglin [3 ]
Spinella, Laura [1 ,2 ]
Im, Jay [1 ,2 ]
Tamura, Nobumichi [4 ]
Kunz, Martin [4 ]
Son, Ho-Young [5 ]
Kim, Byoung Gyu [5 ]
Huang, Rui [3 ]
Ho, Paul S. [1 ,2 ]
机构
[1] Univ Texas Austin, Microelect Res Ctr, Austin, TX 78712 USA
[2] Univ Texas Austin, Texas Mat Inst, Austin, TX 78712 USA
[3] Univ Texas Austin, Dept Aerosp Engn & Engn Mech, Austin, TX 78712 USA
[4] Univ Calif Berkeley, Lawrence Berkeley Natl Lab, ALS, Berkeley, CA 94720 USA
[5] SK Hynix Inc, Icheon Si, Gyeonggi Do, South Korea
基金
美国国家科学基金会;
关键词
X-RAY MICRODIFFRACTION; THERMAL-STRESSES; THIN-FILMS; INTEGRATION; CU;
D O I
10.1063/1.4833020
中图分类号
O59 [应用物理学];
学科分类号
摘要
In this paper, we demonstrated the plasticity mechanism for copper (Cu) extrusion in through-silicon via structures under thermal cycling. The local plasticity was directly observed by synchrotron x-ray micro-diffraction near the top of the via with the amount increasing with the peak temperature. The Cu extrusion was confirmed by Atomic Force Microscopy (AFM) measurements and found to be consistent with the observed Cu plasticity behavior. A simple analytical model elucidated the role of plasticity during thermal cycling, and finite element analyses were carried out to confirm the plasticity mechanism as well as the effect of the via/Si interface. The model predictions were able to account for the via extrusions observed in two types of experiments, with one representing a nearly free sliding interface and the other a strongly bonded interface. Interestingly, the AFM extrusion profiles seemed to contour with the local grain structures near the top of the via, suggesting that the grain structure not only affects the yield strength of the Cu and thus its plasticity but could also be important in controlling the pop-up behavior and the statistics for a large ensemble of vias. (C) 2013 AIP Publishing LLC.
引用
收藏
页数:5
相关论文
共 13 条
[1]   3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration [J].
Banerjee, K ;
Souri, SJ ;
Kapur, P ;
Saraswat, KC .
PROCEEDINGS OF THE IEEE, 2001, 89 (05) :602-633
[2]   Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits [J].
Budiman, A. S. ;
Shin, H. -A. -S. ;
Kim, B. -J. ;
Hwang, S. -H. ;
Son, H. -Y. ;
Suh, M. -S. ;
Chung, Q. -H. ;
Byun, K. -Y. ;
Tamura, N. ;
Kunz, M. ;
Joo, Y. -C. .
MICROELECTRONICS RELIABILITY, 2012, 52 (03) :530-533
[3]  
de Melo J. L. A., 2013, P IEEE INT S CIRC SY, P586
[4]   Cu pumping in TSVs: Effect of pre-CMP thermal budget [J].
De Wolf, I. ;
Croes, K. ;
Pedreira, O. Varela ;
Labie, R. ;
Redolfi, A. ;
Van De Peer, M. ;
Vanstreels, K. ;
Okoro, C. ;
Vandevelde, B. ;
Beynea, E. .
MICROELECTRONICS RELIABILITY, 2011, 51 (9-11) :1856-1859
[5]   Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication [J].
Heryanto, A. ;
Putra, W. N. ;
Trigg, A. ;
Gao, S. ;
Kwon, W. S. ;
Che, F. X. ;
Ang, X. F. ;
Wei, J. ;
Made, R. I. ;
Gan, C. L. ;
Pey, K. L. .
JOURNAL OF ELECTRONIC MATERIALS, 2012, 41 (09) :2533-2542
[6]  
Jiang T., 2013, P IEEE INT TECHN C
[7]   Measurement and analysis of thermal stresses in 3D integrated structures containing through-silicon-vias [J].
Jiang, Tengfei ;
Ryu, Suk-Kyu ;
Zhao, Qiu ;
Im, Jay ;
Huang, Rui ;
Ho, Paul S. .
MICROELECTRONICS RELIABILITY, 2013, 53 (01) :53-62
[8]   3-D silicon integration and silicon packaging technology using silicon through-vias [J].
Knickerbocker, John U. ;
Patel, Chirag S. ;
Andry, Paul S. ;
Tsang, Cornelia K. ;
Buchwalter, L. Paivikki ;
Sprogis, Edmund J. ;
Gan, Hua ;
Horton, Raymond R. ;
Polastre, Robert J. ;
Wright, Steven L. ;
Cotte, John A. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (08) :1718-1725
[9]   Characterization of thermal stresses in through-silicon vias for three-dimensional interconnects by bending beam technique [J].
Ryu, Suk-Kyu ;
Jiang, Tengfei ;
Lu, Kuan H. ;
Im, Jay ;
Son, Ho-Young ;
Byun, Kwang-Yoo ;
Huang, Rui ;
Ho, Paul S. .
APPLIED PHYSICS LETTERS, 2012, 100 (04)
[10]   Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects [J].
Ryu, Suk-Kyu ;
Lu, Kuan-Hsun ;
Zhang, Xuefeng ;
Im, Jang-Hi ;
Ho, Paul S. ;
Huang, Rui .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2011, 11 (01) :35-43