Simplifying HW/SW Integration to Deploy Multiple Accelerators for CPU-FPGA Heterogeneous Platforms

FPGAS became an interesting option for developing hardware accelerators due to their energy efficiency and recent improvements in CPU-FPGA communication speeds. In order to accelerate the development cycle, FPGA high-level synthesis tools have been developed such as Intel HLS, OpenCL, and OpenSPL. These tools aim to free the designer from having to know all the FPGA low-level details. However, in order to achieve high performance processing, the developer should still understand the details of the deeper system layers. Moreover, OpenCL usually consumes more resources/compile time than a design developed directly in RTL. In this work we propose a novel framework to automatically integrate hardware accelerator cores in a final architecture by generating a HW/SW interface for an Intel CPU-FPGA modern platform. Our goal is to simplify the Intel Open Programmable Acceleration Engine (OPAE) by introducing a novel abstraction layer with a simple stream protocol channel. The experimental results for a set of dataflow benchmarks show a performance of up to 131.7 Gops/s, and a power efficiency of up to 353.7 Gops/W even when we bound the memory bandwidth to 12 GB/s.