共 50 条
- [31] YAARC: yet another approach to further reducing the rate of conflict misses The Journal of Supercomputing, 2008, 44 : 24 - 40
- [32] Balanced instruction cache: Reducing conflict misses of direct-mapped caches through balanced subarray accesses IEEE Comput. Archit. Lett., 2006, 1 (2-5):
- [33] A Purely Functional Approach to Packet Processing TENTH 2014 ACM/IEEE SYMPOSIUM ON ARCHITECTURES FOR NETWORKING AND COMMUNICATIONS SYSTEMS (ANCS'14), 2014, : 219 - 230
- [34] METHOD FOR PROCESSING MULTIPLE CACHE LINE MISSES THAT RESULTS IN GREATLY ENHANCING CPU UTILIZATION AND PERFORMANCE. IBM technical disclosure bulletin, 1983, 25 (12): : 6440 - 6442
- [35] Line Replacement Algorithm for L1-scale Packet Processing Cache ADJUNCT PROCEEDINGS OF THE 13TH INTERNATIONAL CONFERENCE ON MOBILE AND UBIQUITOUS SYSTEMS: COMPUTING NETWORKING AND SERVICES (MOBIQUITOUS 2016), 2016, : 12 - 17
- [36] Using packet scheduling to enhance I-Cache behavior of protocol processing Eighth International Conference on High-Performance Computing in Asia-Pacific Region, Proceedings, 2005, : 463 - 468
- [38] Open and reliable group communication processing: The FITOS-RPC approach PROCEEDINGS OF THE SIXTH EUROMICRO WORKSHOP ON PARALLEL AND DISTRIBUTED PROCESSING - PDP '98, 1998, : 389 - 394
- [40] An approach for optimal bandwidth allocation in packet processing systems CNSR 2008: PROCEEDINGS OF THE 6TH ANNUAL COMMUNICATION NETWORKS AND SERVICES RESEARCH CONFERENCE, 2008, : 208 - 214