A 5-b 10-GSample/s A/D converter for 10-Gb/s optical receivers

被引:45
作者
Lee, J
Roux, P
Koc, UV
Link, T
Baeyens, Y
Chen, YK
机构
[1] Bell Labs, Lucent Technol, Murray Hill, NJ 07974 USA
[2] Lucent Technol, Opt Networking Grp, D-90411 Nurnberg, Germany
关键词
analog-to-digital conversion; aperture jitter; comparators; digital equalization; flash converter; optical receiver; polarization mode dispersion (PMD); SiGeBiCMOS integrated circuits; track-and-hold amplifier (THA);
D O I
10.1109/JSSC.2004.833555
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 5-b flash A/D converter (ADC) is developed in an 0.18-mum SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/ - 3 V supplies and occupies 3 x 3 mm(2) of chip area.
引用
收藏
页码:1671 / 1679
页数:9
相关论文
共 15 条
  • [1] [Anonymous], 1995, PRINCIPLE DATA CONVE
  • [2] Equalization and FEC techniques for optical transceivers
    Azadet, K
    Haratsch, EF
    Kim, H
    Saibi, F
    Saunders, JH
    Shaffer, M
    Song, L
    Yu, ML
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (03) : 317 - 327
  • [3] A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS
    Choi, M
    Abidi, AA
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (12) : 1847 - 1858
  • [4] A 10-B, 75-MHZ 2-STAGE PIPELINED BIPOLAR A/D CONVERTER
    COLLERAN, WT
    ABIDI, AA
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (12) : 1187 - 1199
  • [5] A 10-BIT 5-MSAMPLE/S CMOS 2-STEP FLASH ADC
    DOERNBERG, J
    GRAY, PR
    HODGES, DA
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (02) : 241 - 249
  • [6] A 10-BIT 60 MSPS FLASH ADC
    LANE, C
    [J]. PROCEEDINGS OF THE 1989 BIPOLAR CIRCUITS AND TECHNOLOGY MEETING, 1989, : 44 - 47
  • [7] A 6-b 12-GSamples/s track-and-hold amplifier in InP DHBT technology
    Lee, J
    Leven, A
    Weiner, JS
    Baeyens, Y
    Yang, Y
    Sung, WJ
    Frackoviak, J
    Kopf, RF
    Chen, YK
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (09) : 1533 - 1539
  • [8] AN 8-BIT 200-MHZ BICMOS COMPARATOR
    LIM, PJ
    WOOLEY, BA
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (01) : 192 - 199
  • [9] A 400-MHZ INPUT FLASH CONVERTER WITH ERROR CORRECTION
    MANGELSDORF, CW
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (01) : 184 - 191
  • [10] Murata K., 1994, P IEEE GAAS IC S, P193