On-chip sampling in CMOS integrated circuits

被引：17

作者：

Delmas-Bendhia, S ^{[1
]}

Caignet, F

Sicard, E

Roca, M

机构：

[1] Inst Natl Sci Appl, DGEI, Dept Elect & Comp Engn, F-31077 Toulouse 4, France

[2] Univ Balearic Isl, Dept Phys, Palma De Mallorca 07071, Spain

来源：

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY | 1999年 / 41卷 / 04期

关键词：

crosstalk delay; crosstalk effects; crosstalk measurements; electromagnetic compatibility in integrated circuits; sampling sensors;

D O I：

10.1109/15.809837

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a technique for precise crosstalk delay measurement based on on-chip sampling. Results obtained on a test chip fabricated in 0.7-mu m CMOS technology exhibit a 100% delay increase in a long coupled line configuration.

引用

页码：403 / 406

页数：4

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