Soft error rate scaling for emerging SOI technology options

被引：17

作者：

Oldiges, P ^{[1
]}

Bernstein, K ^{[1
]}

Heidel, D ^{[1
]}

Klaasen, B ^{[1
]}

Cannon, E ^{[1
]}

Dennard, R ^{[1
]}

Tang, H ^{[1
]}

Leong, M ^{[1
]}

Wong, HSP ^{[1
]}

机构：

[1] IBM Corp, SRDC, Hopewell Jct, NY 12533 USA

来源：

2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIT.2002.1015382

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The soft error rate in SOI devices is explored. Conventional SOI device soft error rate is compared to high mobility SOI and double gate SOI designs. We develop a theoretical understanding of the susceptibility of SOI devices to alpha-particle induced soft errors by means of simulations and measurements. Although high mobility devices will decrease soft error rate susceptibility, silicon thinning is shown to have a much larger impact. Double gate devices are shown to improve the soft error rate even further.

引用

页码：46 / 47

页数：2

共 14 条

[1]

BUTURLA E, 1989, NASCODE, V6, P291

[2]

Chau R., 2001, IEDM, P621

[3] Impact of CMOS process scaling and SOI on the soft error rates of logic processes [J].

Hareland, S ;

Maiz, J ;

Alavi, M ;

Mistry, K ;

Walsta, S ;

Dai, CH .

2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2001, :73-74

[4] Carrier mobility enhancement in strained Si-On-Insulator fabricated by wafer bonding [J].

Huang, LJ ;

Chu, JO ;

Goma, S ;

D'Emic, CP ;

Koester, SJ ;

Canaperi, DF ;

Mooney, PM ;

Cordes, SA ;

Speidell, JL ;

Anderson, RM ;

Wong, HSP .

2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2001, :57-58

[5]

Ieong M., 2001, IEDM, P441

[6]

Kedzierski J., 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), p19.5.1, DOI 10.1109/IEDM.2001.979530

[7] MONTE-CARLO ANALYSIS OF SEMICONDUCTOR-DEVICES - THE DAMOCLES PROGRAM [J].

LAUX, SE ;

FISCHETTI, MV ;

FRANK, DJ .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1990, 34 (04) :466-494

[8]

Leong M. K., 1998, Simulation of Semiconductor Processes and Devices 1998. SISPAD 98, P129

[9] Parasitic bipolar gain reduction and the optimization of 0.25-μm partially depleted SOI MOSFET's [J].

Mistry, KR ;

Sleight, JW ;

Grula, G ;

Flatley, R ;

Miner, B ;

Bair, LA ;

Antoniadis, DA .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (11) :2201-2209

[10] Soft-error Monte Carlo modeling program, SEMM [J].

Murley, PC ;

Srinivasan, GR .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1996, 40 (01) :109-118

← 1 2 →