Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks

被引：8

作者：

Eckert, Charles ^{[1
]}

Wang, Xiaowei ^{[1
]}

Wang, Jingcheng ^{[2
]}

Subramaniyan, Arun ^{[1
]}

Iyer, Ravi ^{[3
]}

Sylvester, Dennis ^{[4
]}

Blaauw, David ^{[5
]}

Das, Reetuparna ^{[1
]}

机构：

[1] Univ Michigan, Dept Comp Sci & Engn, Ann Arbor, MI 48109 USA

[2] Univ Michigan, Dept Elect Engn & Comp Sci, Ann Arbor, MI 48109 USA

[3] Intel Corp, Santa Clara, CA 95051 USA

[4] Univ Michigan, Elect Engn & Comp Sci, Ann Arbor, MI 48109 USA

[5] Univ Michigan, Ann Arbor, MI 48109 USA

来源：

IEEE MICRO | 2019年 / 39卷 / 03期

关键词：

D O I：

10.1109/MM.2019.2908101

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This article presents Neural Cache architecture, which repurposes cache structures to transform them into massively parallel compute units capable of running inferences for deep neural networks. Techniques to do in situ arithmetic in SRAM arrays create efficient data mapping, and reducing data movement is proposed. Neural Cache architecture is capable of fully executing convolutional, fully connected, and pooling layers in cache. Our experimental results show that the proposed architecture can improve efficiency over a GPU by 128 x while requiring a minimal area overhead of 2%.

引用

页码：11 / 19

页数：9

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