Smart-Eyes: a FPGA-based smart camera platform with efficient multi-port memory controller

In this paper, a FPGA-based smart camera platform is proposed. A Xilinx FPGA has been adopted as the core device. Xilinx ISE Design Suite has been used as the design tool and Verilog as the program language. In order to validate the platform, two real-time demonstrations have been implemented. In order to achieve a better tradeoff between performance and power consumption, a novel Multi-Port Memory Controller (MPMC) has been proposed. With a new memory mapping method and prefetching mechanism, the proposed MPMC outperforms Xilinx's MPMC (at least 25% optimization) in terms of data access. Additionally, the utilization of hardware resources of the FPGA is less than 5%. Thus the proposed Smart-Eyes can be further adopted in many reasonable real-time algorithms and applications.