FPGA Based Arbiter Physical Unclonable Function Implementation with Reduced Hardware Overhead

被引：0

作者：

Ivaniuk, Alexander A. ^{[1
]}

Zalivaka, Siarhei S. ^{[1
]}

机构：

[1] Belarusian State Univ Informat & Radioelect, Minsk 220013, BELARUS

来源：

PATTERN RECOGNITION AND INFORMATION PROCESSING, PRIP 2019 | 2019年 / 1055卷

关键词：

Physical Unclonable Function; Arbiter; FPGA; LUT; Symmetrical path;

D O I：

10.1007/978-3-030-35430-5_18

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The existing implementations of the arbiter physical unclonable function (PUF) are based on synthesis of configurable symmetric paths, each link of which is a pair of two-input multiplexers providing two configurations of test signal translation: straight and exchange. To build a single link on FPGA, it is necessary to use two built-in LUT blocks, providing the implementation of two multiplexers, and the hardware resources of the LUT blocks are not fully utilized. The paper presents a new architecture of symmetric paths of the arbiter PUF, providing efficient use of the hardware resources of LUT blocks for various Xilinx Artix-7 FPGA family.

引用

页码：216 / 227

页数：12

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